I’m cross-referencing the TRMs with the DSI patent by looking at how the addressing scheme connects the two in a way that makes mathematical sense… and well, I can now compile an XOR gate from gForth to the UDB + routing/DSI system and light up the blue led when I set either of the input pins with my Bus Pirate.
As I had hoped, the PLDs are also reconfigurable during operation, not just the DSI through the Dynamic Configuration RAM.
At first I tried to halt the PSoC before writing the configuration bytes over SWD. But for this to work, I needed to wipe the entire PSoC and write the configuration bytes over SWD without halting.
I used the mostly complete (?) openocd support for the KitProg and PSoC 5LP (by cyrozap and Andreas Färber) to read and write the configuration bytes from extensible Forth over the tcl rpc interface.
I’ve been doing a deep brainstorm on how best to factor the UDB, Routing, and DSI code such that it will work well for partial dynamic live reconfiguration, or in a way, compiling Forth words to Boolean algebra (the CPLD) from the interpreter. Once I’ve figured more of that out, cleaned-up my experiments, and reached some stability in my approach I think I can release the code to the world. Huzzah! Thanks for reading!